Application Note 1165
FIGURE 11. SCREEN SHOT OF THE CONFIGURATION TAB
Configuration Tab
This tab allows the user to adjust the XSD bus voltage.
Eventually, this tab will also allow the user to download new
firmware to the interface board for upgrading. The latter
function is not implemented at this moment.
Evaluation Waveforms
The digital signals transferred over the XSD bus can be
verified with the help of an oscilloscope. The XSD bus has
three digital signals, logic ‘1’, logic ‘0’ and ‘break’. Each bit of
the digital signals starts with a falling edge. The logic ‘1’ is
represented with a signal whose rising edge occurs at
approximately 30% of the bit time (BT). The logic ‘0’ has a
rising edge occurring at about 70% of BT. A ‘break’ signal is
one whose rising edge happens after 1BT.
Bit ‘1’ and Bit ‘0’
Figure 12 shows the waveforms for the XSD bus during a
transaction. The lower half is a zoomed-in view of the portion
of the upper waveform inside the rectangular dash-line box
and illustrates how the XSD signal is implemented. The first
bit being sent out is the least-significant bit (LSB) of a byte.
7
Figure 12 was captured when the XSD bus was reading 4
bytes of data from the ISL6296 EEPROM. The “A” section of
the upper waveform is the 16-bit instruction frame. The “B”
section is the 4 bytes from the ISL6296. From the waveform,
one can tell that the chip selection field CS = ‘0’, the
OPCODE = ‘01’, the address bank BANK = ‘00’ (EEPROM),
and the address = ‘...01010’. The total byte number is out of
the zoomed-in window but it was ‘100’ (4 bytes).
A Complete XSD Transaction
Figure 13 demonstrates a complete XSD transaction of
reading the MSCR and STAT registers. The instruction frame
for reading these two registers are given in Table 2. Starting
from LSB, the instruction frame is: ‘0, 10, 10, 0000, 0000,
010’. This matches the signals from the scope. Also from the
scope waveform, the MSCR and STAT are found out to be,
starting from LSB, ‘0000, 0011’, and ‘0000, 0000’ respectively
(see Figure 13). Using the XSD Access Tab in the software,
the MSCR will be filled into Byte 1 of the table and STAT will
be filled into Byte 2. From the MSCR register, one can tell that
the Autosleep (ASLP) bit is ‘0’, meaning the auto-sleep mode
is turned off.
AN1165.1
July 14, 2009
相关PDF资料
ISL6298EVAL1 EVALUATION BOARD 1 ISL6298
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